Posts by pwsoft

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    How about instead of creating a c128 core, you could just implement a “c128 in C64 mode” core which would mean having vdc available in software like novaterm/striketerm. You wouldn’t create a new machine, but give 64 users the ability to have higher resolution/text.

    Even ignoring for a moment the relative large amount of development effort for only a handful of programs (while that time could be spend on fixing bugs in the C64 part of the design instead for example). The current architecture simply isn't capable of displaying 80 column text or the required 640 pixels. The framebuffer logic that eventually creates the VGA display only supports 400-ish pixels in horizontal direction (with 16 colors). I did play with ideas like that the past, but for example SID emulation that wasn't planned originally uses up most of the previously unused FPGA logic now. So each time a new proposal like a VDC (or for example SCPU as a recurring theme) it is always a question what can be removed to make room. Answer probably is nothing. I don't want to remove 1541 emulation or SID emulation or the whatever other feature added with good reason to make room for a VDC that only a handful of programs are going to use. Yes you could make multiple cores each with a sub-sets of features, but that will surely disappoint somebody somewhere as (s)he wants VDC plus whatever feature that was axed.

    Ports on pin-headers where customers make their own "solutions" to connect to existing hardware sounds like a support nightmare waiting to happen. I guess for adventures in a complete custom C64 like that, the Turbo Chameleon+docking-station is a possible starting point. Small enough that it can be modded into whatever.

    Computer says no.

    Code
    1. Error (170040): Can't place all RAM cells in design
    2. Info (170034): Selected device has 66 memory locations of type M9K. The current design requires 80 memory locations of type M9K to successfully fit.
    3. Info (170033): Memory usage required for the design in the current device: 121% M9K memory block locations required

    With the recent SID improvements it no longer fits on the C-One without some big changes to the way it boots or disabling these new features (which defeats the purpose of releasing such an update). So I tried, but really can't spend more time on it. Other projects have priority as you hopefully can understand.

    Why is there an Intel cyclone chip on the picture of the card? Is it only for the prototype? I thought the point of you card versus, for example the vampire accelleration cards, is that there is no FPGA emulation being used.

    The fact that we use a real CPU doesn't mean there isn't other logic functions that need to be performed. The main purpose of the FPGA is being the memory controller for the zorro III compatible ram on board. It will also contain a lot of logic for example to talk "Amiga" as that talks 020 bus, which isn't directly compatible with 040/060 bus. In the past this logic would have typically been implemented with CPLDs or PALs/GALs and maybe a Motorola glue chip like the MC68150 (which is nowadays nowhere to be found). Compared with that method, FPGAs have the advantage that it is RAM based, so allow for firmware updates to provide fixes and improvements "in the field". And they have much more logic allowing more features to be packed on a small board. We also use the PLLs in the FPGA to generate the various clocks, like PCLK and BCLK for the 040 CPU.

    So the Turbo Chameleon isn’t a retro product either?

    Some would say anything with a VGA output is retro. The design of the Chameleon is now 10 years old, is that enough time passed for it to become retro? Dunno. Maybe we should call these things "retro-compatible" products, until enough years have passed.

    I would absolutely love to see a 128 core, but I know I am in rare company. I'm one of the few people who appreciate the VDC.

    What I would think should be more realistic? A SuperCPU core maybe?

    Yes the VDC properties are nice (though glitch-y), the rest of the 128 architecture is a bit of a mess unfortunately. Building a accurate replica with all the quirks will be a nightmare. And because the Chameleon hardware itself doesn't work on a C128, we kind of try to ignore this topic ;-)


    A SuperCPU comes up quite often in discussions. However if you look realistically there are only a handful of programs that really use the 16 bit instruction set of the 65816 processor. Most of the SuperCPU titles just want the faster speed that is already covered with the existing turbo functionality. Designing a new core for running just two extra programs is a bit meh.

    The value of 20h displayed for SID2 is considered "empty" socket by the firmware. So I can imagine why that gives a flashing led when put in socket position for SID 1. It is invisible to the board.

    I can not really recommend using this "pin removal" procedure on the mk2. As it can cause the automatic chip detection to fail resulting in a flashing green LED.

    For this function to work, both the drive emulation needs to be enabled AND the left button needs to be set to the drive you want to use multiple disks function for. So for drive 8 to have multiple disks, go in the options to Button Settings and set Left Button to "disk drive 1". Then go back to file browser and press commodore key (alt on ps/2) + M to mount disk images. Once you press cbm+M the second time a menu pops up asking in which slot to mount the image.


    When playing a game or demo and the request comes to swap the disk press the left button on the chameleon. Short press goes to next disk image in the list. Long press always goes to the first image.

    I can think of two things the Indivision V2 does differently from a real Denise.

    The first one is easy to check. The Genlock Audio bit is used to enable Graffiti emulation, I guess that feature should be switched off (not sure what the default configuration is), when doing GenLock thingies.


    The other might be a missing feature for the ZD (background indicator) pin in the emulation. Not sure if (and if yes? how) the video toaster would use this pin. This is ZD pin of Denise is connected to pin 14 (called PIXLSW) on the RGB output. Especially for ECS version of the Denise this pin can have a thousand and one different functions, not all emulated. One function is to determine what is background and what is foreground in the Amiga picture.


    I admit I don't know how the video toaster works on hardware level, so hard for me to tell what it fails to find exactly at this moment.

    The only reason I can think of both CIAs are affected, but still have VIC-II is if U15 an 74hct139 selector is broken. That same chip also controls DExx and DFxx. So you could check with a freezer cartridge if it can "freeze" into its menu to verify that it still works.


    Just to exclude the obvious though. You did observe the correct orientation of the CIA chips.. right? Notch on the chip on the same side as the metal handle/lever on the ZIF-socket. I do say this, because the text on the CIAs will be upside down, which isn't the way you expect then to go in, maybe.

    Recommending FPGA development boards falls a bit outside the scope of this icomp product support forum. Inside icomp we use Altera/Intel FPGAs (specifically the Cyclone series) exclusively, so I don't have any recent experience with the other vendors.


    If just starting out with HDL, I think selecting the C64 as direct end goal is a bit hmmm... optimistic? Because the machine uses custom chips for most of the tasks (memory mapping, video, audio) it is quite a few levels above logic gates and multiplexers. You need a large amount of logic infrastructure before you even get a READY prompt. And that is just the start, then you get into the debugging and getting the details right (for me a journey of about 14 years and counting)

    As a side note. The FPGA on the Chameleon has about 6 times the logic capacity compared to the FPGA chips used on the original C-One board. So with only a very base system (just the CPU, VIC-II and RAM) the C-One was essentially already full. The extender that came out later resolved some of the constraints, but programming the C-One still was a bit of challenge, due to the need to create 2 or 3 different FPGAs images for each design. And some of the design choices made on the board were hmm, how should I describe them... unfortunate.


    Chameleon project started as just a video card for the C64 (originally called vga64) and then it met a thing called "feature creep" and now it is what it is ;-) A very versatile retro emulation platform in a C64 cartridge.

    Please don't do that, we don't need the extra noise in the forum. Keep in mind icomp is in holiday mode (until 9th of august) as noted on the shop news page. So little patience please... not everybody is available at the moment to answer your questions. Thanx

    According to https://www.sidfx.dk/details

    SIDFX can be configured to map SID 2 at either $D420, $D500 or $DE00. These are the typical address spaces used for stereo SID tunes. While in mono mode SID 2 resides at $D400.


    Website doesn't specify how that selection is made, but any of the addresses should work with Chameleon without any problems if matched in "Real Stereo SID" setting of Chameleon.