List of FPGA cores that could be ported to Chameleon hardware

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  • Over the last few weeks I've picked up enough x86 assembly to make some changes to the bootloader and BIOS, and spent some time adding my usual ZPU-based control module to the project.

    Wow - that's a ton of work, and exactly the path we've discussed here. Should I say "great minds think alike" :-)?


    Does one of the many sound cards of the Next186 core have a MIDI interface? If so, the new Docking Station will come in handy.

  • Does one of the many sound cards of the Next186 core have a MIDI interface? If so, the new Docking Station will come in handy.


    Not yet, but I don't think there'd be much to adding dumb-mode MPU401 beyond sticking a 31250baud UART on port 330/331 and hooking up an interrupt.


    Adding support to the Minimig core should be simple, too - Bars and Pipes is still awesome!

  • Here's a pre-alpha release of the Next186 core

    http://retroramblings.net/snap…_Chameleon_2019-09-15.zip


    The zipfile contains binaries for both V1 and V2, along with a BIOS and an optional freedos boot image. The BIOS must be on the SD card (at least the one you boot with). You can boot directly from the SD card if you wish, but if you're using FreeDOS the first partition must be FAT16 formatted, because the FreeDOS FAT32 bootloader requires a 386 CPU. If the boot disk image is on the SD card then it can be FAT32 formatted; the boot code will come from the floppy disk image.


    Known problems:

    • There's no error handling or display of error messages for the disk image support or BIOS loading
    • The core sometimes comes up with a shifted or scrambled display. I don't yet know what's causing this, but I suspect it's to do with phase relationships between the core's multiple clocks, since resetting the core doesn't fix it.
    • The OPL3 emulation doesn't start properly on V1 hardware. I have no idea why this doesn't affect V2 hardware or the development Cyclone III board I've been using - the only thing V2 and the dev board have in common is that they have an off-chip 50MHz clock source, which is used by the OPL3, while the V1 hardware has to generate it in a PLL along with all the other clocks. I've tried many things to fix this, including adjusting the 50Mhz clock's speed and phase, synchronising, adding and removing reset signals - but the problem resolutely remains. As a workaround, I've mapped the Freeze button to a separate reset for the OPL3 emulator; pressing this usually causes it to spring into life.

    Source is at: https://github.com/robinsonb5/Next186_SoC