first, i noticed when playing with the remote, the values in the second and third block are changing with some delay to the first block... sometimes
OK well the idea with the second and third block is that the second one will latch any recently seen zero bits, while the third block latches recently seen high bits - both are reset every second or so, on a fixed shedule for simplicity's sake, so it's normal for the delay to vary. The idea is just to make brief transients readable, since we don't have the luxury of signaltap here.
then... now that you asked for the fourth row, i noticed something else: when i run the core using chaco (power up, then use chaco to start the core slot) the third and fourth row are all zeros (and do not change ever). now, if i select the core in the chameleon menu, the third and fourth row will contain somehwhat random values (that dont change either) - but ONLY if there is a sd card inserted when the core starts. when i remove the sd card before, the values will also be all zeros.
That's *very* weird. Is there a schematic available for the V2 hardware?
OK let's go right back to basics here. Here's a build of Peter's hardware test core, which he updated recently to fix the transients I was seeing on my setup. So this is the same version of the IO module, built with the same version of Quartus as the PCEngine core. Could you just double check that this works correctly on your machine, please?