Hi. I have an RTC clock module that I'd like to fit to an ACA 500 plus. I'm not sure of the orientation on the board. It could fit one of two ways. Can you please point me to a picture showing me how to install it. Thanks.
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Hello
This is how I use it
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Thank you.
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confirmed efren's orientatino. Another hint: The connector for the X-Surf-500 would be covered if the RTC module was installed the other way round, so that does not make a lot of sense.
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Just going to say that the RTC module extending beyond the edge of the ACA500 makes the idea of a nicely fitting case a nightmare.
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Just going to say that the RTC module extending beyond the edge of the ACA500 makes the idea of a nicely fitting case a nightmare.
...which is why the ACA500plus supports the RTC in two more places: The trapdoor memory expansion and the A1200 accelerator.
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The RTC module looks *MUCH* more at home fitted on the aca1221ec (or the trapdoor mem expansion) than the aca500+
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It's the same pinout as on the A1200 computer.
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Jens the best documentation i see on this is here (and i even downloaded the clk_serial.lha archive and read it thoroughly):
http://www.ianstedman.co.uk/Am…lock_port/clock_port.html
and it's not very clear how those 40 pins map to the 22 pin connector. Would you be so kind as to point me where to look for a definitive pinout that maps the 22 pin ACA500plus clock connector to the A1200 clock port?
thanks.
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Ok, I think I figured it out, the key was in this sentence of the above doc that I posted: "Note that only the P9B pins 19-40 actually have a header soldered in in most machines"
This seems to make sense because the header is 22 pins... Jens is this correct?
Display MoreCode- 19: GND Ground
- 20: VCC +5v DC
- 21: INT6 Interupt Request
- 22: _SPARE_CS
- 23: _RTC_CS Real Time Clock CS
- 24: _PWR_BAD
- 25: _IORD IO Read
- 26: _IOWR IO Write
- 27: A5 Address Bus Bit 5
- 28: A4 Address Bus Bit 4
- 29: A3 Address Bus Bit 3
- 30: A2 Address Bus Bit 2
- 31: D23 Data Bit Bit 23
- 32: D22 Data Bit Bit 22
- 33: D21 Data Bit Bit 21
- 34: D20 Data Bit Bit 20
- 35: D19 Data Bit Bit 19
- 36: D18 Data Bit Bit 18
- 37: D17 Data Bit Bit 17
- 38: D16 Data Bit Bit 16
- 39: GND Ground
- 40: _RESET Reset
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Haven't verified each pin, but that looks correct. Note that the PWR_Bad signal is not available on the ACA500plus (and it may even be unavailable on the A1200; I've never seen anything that uses it).
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The clock port is 2.00mm pitch.
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The last reply was more than 365 days ago, this thread is most likely obsolete. It is recommended to create a new thread instead.
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