Hi Jens, thanks for the prompt reply. Looking at the results of the bustest it appears to be working properly. Here are the results:
BusSpeedTest 0.19 (mlelstv) Buffer: 262144 Bytes, Alignment: 32768
========================================================================
memtype addr op cycle calib bandwidth
fast $40890000 readw 130.0 ns normal 15.4 * 10^6 byte/s
fast $40890000 readl 155.2 ns normal 25.8 * 10^6 byte/s
fast $40890000 readm 144.3 ns normal 27.7 * 10^6 byte/s
fast $40890000 writew 78.6 ns normal 25.4 * 10^6 byte/s
fast $40890000 writel 79.5 ns normal 50.3 * 10^6 byte/s
fast $40890000 writem 74.2 ns normal 53.9 * 10^6 byte/s
chip $00018000 readw 575.8 ns normal 3.5 * 10^6 byte/s
chip $00018000 readl 577.9 ns normal 6.9 * 10^6 byte/s
chip $00018000 readm 617.8 ns normal 6.5 * 10^6 byte/s
chip $00018000 writew 576.0 ns normal 3.5 * 10^6 byte/s
chip $00018000 writel 578.8 ns normal 6.9 * 10^6 byte/s
chip $00018000 writem 579.0 ns normal 6.9 * 10^6 byte/s
rom $00F80000 readw 129.6 ns normal 15.4 * 10^6 byte/s
rom $00F80000 readl 155.2 ns normal 25.8 * 10^6 byte/s
rom $00F80000 readm 144.5 ns normal 27.7 * 10^6 byte/s