Adding a missing feature to MK2 :)

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Don't Panic. Please wash hands.

    We have 2 SIDs, but only one VICII, so i decided to fix it. And it works! This addon board allows to switch between NTSC and PAL VICII. It's nice MK2 has no capacitor on RESTORE key, so i can use this key directly on startup. If RESTORE key is holding down when powering on, then board switches to alternative VICII, otherwise it uses the chip selected before.


    Nope. I'm muxing only 2 analog outputs and power. All other pins are simply connected together and don't interfere when chip is powered off. I've saw such mod using tumblers. So i've decided to make similar one using modern chips.

    Well, it's still in testing stage, but it seems has no problem.

    This does not sound like a "known good design" - the current draw on the unpowered VIC is not specified. How do you power down? Do you lower the Vcc part to GND, or do you tie the GND pin to Vcc?

    Yes, i know it's not how correct design should look like. Muxing ~40pins will require quite complex routing and many analog switches.

    For one VIC I tie VCC to GND by 1K pull-down resistor to make sure another MOSFET is switched ON. Another VIC's power is not tied to GND at all. I'm using MOSFETs as high-side power switches.

    Probably it's good to measure each pin current drown by supplying logic 1 to unpowered VIC.

    Just thought, may be it's better to select VICs by GND pin. Pulling up inactive VIC's GND to VCC by resistor will make just additional possible pulling up on digital pins which is normal for bi-directional bus.

    That's what I was initially thinking - hence my question how you're powering down. However, it may be a good idea to reverse-engineer the IO stages of those HMOS chips to actually *calculate* what's happening, instead of just trying. I really prefer the engineering approach over the "but it works!"-screamers who never want to hear about fundamentals.

    After study datasheet, i think it's not a good idea to select VICII by GND pin as max negative rating on pins is -0.5V while max positive rating is +7.7V. I think internal mosfets don't made for large negative voltage, so better to use VCC as a selector. It should be not so hard to use natural tri-state bus mode of VICII by holding the input clock at right moment. This way power consumption will be approximately doubled because even non-clocked VICII will consume almost full power since it's NMOS/HMOS, not CMOS.

    Max positive rating 7.7V means that it's only 2.7V above VCC. This means that during operation with VCC=0V, the IO pins should not rise above 2.7V.


    Can you ensure that?

    I think you are wrong. It's not calculated like that. If max rating is related to VCC then it would be written as VCC+2.7V. If it's written as absolute 7.7V then it's simply 7.7V regardless VCC which has it's own max rating.

    That's not supported by the basic principles of semiconductors. While you're right that the datasheet doesn't write it as "VCC+2.7V", I'd be very careful insisting that this can be read like it's tolerant to VCC+5V without knowing the exact circuit or having made measurements that support the claim.


    Since clamping diodes at the IO pins are not present on NMOS chips, this most-simple bullet poiint can be eliminated. So "measuring" would be the next step. Shouldn't be too hard - I'd take a 1MOhms resistor, apply 5V through it to an unpowered (but grounded) VIC chip's IO and measure the voltage at the IO pin. If it's sufficiently-high, you can assume that it won't cause damage. After all, to cause damage you need power, and you don't have that on the other side of the 1MOhms resistor :-)

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