New Buster chip

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Don't Panic. Please wash hands.
  • Wie so viele Dinge ist auch dieses Projekt von der "chip shortage" betroffen. Ich kann derzeit nicht einmal einen Prototypen bauen, so dass die Entwicklung rein virtuell stattfindet.

  • And if the 16MHz A3000 is equipped with G-Force 040?


    ...then it should be no problem to set the jumpers to 25MHz board clock - that will also increase Z3 performance.

    Agreeing on the performance boost using 25MHz vs 16MHz, and RAMSEY access will likely improve, but I believe the CPU/FPU will still get those faster clocks, no?

    Former GVP Tech Support 1989-93, GuruROM Maker/Supporter (as personal time allows)

  • but I believe the CPU/FPU will still get those faster clocks, no?

    Since there's an accelerator in most of those systems, that's not a problem at all. Further, all the 16MHz A3000 computers that I have seen so far were fine being overclocked to 25MHz. I have yet to see a CPU that a) can't take the overclocking and b) causes trouble when an accelerator is active (they are tri-stated in those cases).


    If any of these observations were wrong, there would be a need to support 16MHz operation. At this point, I don't see it.

  • Nope - we'll have to re-do all the hardware, as the Max-V chip that I initially planned is not going to be available before 2024. This chip crisis keeps delaying things...

  • Nope - we'll have to re-do all the hardware, as the Max-V chip that I initially planned is not going to be available before 2024. This chip crisis keeps delaying things...

    I'm about to build my next re-amiga - the A4000TX ;)

    I got the A4000 chipset from icomp (very good price btw) but I'm going to need "a" Buster. They are impossible to source at any realistic price.


    Do you think we'll see a Buster V12 this year?

  • I may have a prototype later this year, but they are not going to be for sale. I was thinking of offering the -9 Buster chips for sale, so DIY-projects like yours can at least test what they have achieved so far.

  • I may have a prototype later this year, but they are not going to be for sale.

    That is progress :) Can't rush quality

    I was thinking of offering the -9 Buster chips for sale, so DIY-projects like yours can at least test what they have achieved so far.

    That sounds very nice. Just say when and where and I'll order right away.


    When the v12 becomes available I'll order that too :) I have a CV64 i bought back in 95 and i remember that it required a v11 - but anything else should be somewhat ok on v9

  • Buster-9 works with just about anything, unless it's a DMA card. For an A4000T, there's the on-board SCSI controller that will do Z3 DMA, so that machine either *requires* the -11 or higher Buster, or you skip on the on-board SCSI completely, then the -9 Buster would be fine.

  • Most of my understanding of the Buster chip behavior is from Dave Haynie's notes from back in the day:


    http://wonkity.com/~wblock/a4000hard/defibust.html


    The -09 seems to be okay for Z2, and unrelated forum posts I recall since have implied the -09 might even be better fit than -11 for the 16MHz A3000D models in some cases,. but Dave's notes imply fixes included in -11 for the A4000-series related to Z3 expansion bus.


    From personal reading of the forums over the years, the use of an accelerator on any machine can muddy the waters. Each design, being different, can load some unbuffered bus signals in different ways, and affect Buster, Gary, or other chips' timing slightly. The lack of resources Dave noted back in the day made for some uncertainties which could not be well tested, and the too-old adage 'YMMV' has to be applied.

    Nevertheless, I am also interested in a -12 (or whatever it's deemed) if/when it can be produced.


    One thing I am interested in (at some point) is to understand where Buster comes into play when there is a 57C710 on the motherboard (i.e. - A4000T), and/or there is a similar/identical 53C7xx chip on a CPU slot accelerator (P5, TekMagic, a few others?) in the A4000D/T - what part does Buster play in managing or cooperating with this additional busmaster on the CPU-side?

    Former GVP Tech Support 1989-93, GuruROM Maker/Supporter (as personal time allows)

  • what part does Buster play in managing or cooperating with this additional busmaster on the CPU-side?

    Buster controls bus timing for all the different cases of "data source" vs. "data destination". With DMA on Z3, there are several sources (not just the CPU), and with Z3, SCSI, on-board RAM and off-board RAM, there are multiple destinations as well. In theory, these are all asynchronous operations, which need to be handled as such. With the limited time and logic ressources Dave had back in the days, I find it impressive that after only eleven iterations, they had a chip that has held up quite well over the years. Granted, DMA from Z3 to accelerators is kinda-broken, and two Z3 bus masters can stall each other, but it's still impressive, given the tools in the 1990s were far from what we have available today.


    My recent rant against Xilinx and Altera (now AMD and Intel) was (in part) triggered by my disappointment about them being unable to deliver, and even not able to give a delivery date, although I have a project that *should* be interesting enough for an FPGA manufacturer. Looks like I'll go "Asian FPGA" for the Buster-12 project. I hope Dave doesn't mind - when we agreed on the cooperation, it was clear that I'll use Altera, but after all these years of being unable to even make a prototype, I'm so pissed with the big western FPGA makers that all my loyalty is gone.


    Jens

  • Buster controls bus timing for all the different cases of "data source" vs. "data destination".

    I realize this is kind of tangent...among the curiosity of that explanation, I know that the TekMagic/GVP T-Rex II 68060, with it's 53C710, doesn't like the A4000T's 53C710 being there. The same basic card, the Ultrasound version, without the SCSI interface, runs without issue. I'm curious if any other A4000D-targeted accelerators with SCSI on them have a similar conflict in the A4000T? and if Buster would have any say in the matter?


    I agree that Dave did a very good job considering the (lack of) resources available.

    Former GVP Tech Support 1989-93, GuruROM Maker/Supporter (as personal time allows)

  • I'm curious if any other A4000D-targeted accelerators with SCSI on them have a similar conflict in the A4000T? and if Buster would have any say in the matter?

    I can only speculate here, as the only accelerators for A4000/A3000 that I have ever seen are the Apollo accelerators with their semi-SCSI (lots of software with a tiny bit of hardware support). This does not conflict with the on-board SCSI of the A4000T, but that may have to do with the fact that the developer has developed against the Fastlane Z3, which is essentially a Commodore 4091, which in turn is what the SCSI on the A4000T main board is.


    Long story short: Phase5 stopped making the Fastlane Z3 controller, because it didn't work properly with their own accelerators, and people started suggesting to each other to go for the Apollo one, recommending the right memory SIMMs and to not even think about using the on-board SCSI. So even Phase 5 had their trouble with Z3 DMA and the different Buster revisions. I can't say if it'll be possible to make that all work with the Buster-12.


    Jens

  • Thanks for the speculation. An item possibly for Dave to consider at some point, or at least offer an opinion - if he chooses.

    Former GVP Tech Support 1989-93, GuruROM Maker/Supporter (as personal time allows)